Integrated circuits include input pins for receiving signals from the outside world and output pins for providing signals to the outside world. Since integrated circuit packages are advantageously compact, increasing the number of pins means increasing the integrated circuit packaging size and cost.
For example, when testing integrated circuits, a number of modules or components may be scanned or analyzed for errors or defects. The more scan chains of modules to be analyzed, generally the more pins that are needed to receive signals from those scan chains. Conversely, the longer the scan chains, the slower the testing process. Either way, the costs may be aggravated.
Single level compaction has been used to achieve up to an order of compaction in the number of scan output pins that need to be observed. A single level compactor is difficult to extend to devices having multiple cores or for system on chip (SOC) designs.